1. Field of the Invention
This invention relates generally to producing a local clock synchronized in frequency and phase to a reference clock, and more particularly, to producing the local clock by delaying the reference clock.
2. Description of the Related Art
In synchronous systems, the integrated circuits in the system are synchronized to a common reference clock. This synchronization often cannot be achieved simply by distributing a single reference clock to each of the integrated circuits for the following reason, among others. When an integrated circuit receives a reference clock, the circuit often must condition the reference clock before the circuit can use the clock. For example, the circuit may buffer the incoming reference clock or may convert the incoming clock from one voltage level to another. This processing introduces its own delay, with the result that the processed reference clock, which will be referred to as a local clock, often will no longer be adequately synchronized with the incoming reference clock. The trend towards faster system clock speeds flirter aggravates this problem since faster clock speeds reduce the amount of delay, or clock skew, which can be tolerated.
To remedy this problem, an additional circuit is typically used to synchronize the local clock to the reference clock. Two common circuits which are used for this purpose are the phase-locked loop (PLL) and the delay-locked loop (DLL).
In the phase-locked loop, a voltage-controlled oscillator produces the local clock. The phases of the local clock and the reference clock are compared by a phase-frequency detector, with the resulting error signal used to drive the voltage-controlled oscillator via a loop filter. The feedback via the loop filter phase locks the local clock to the reference clock. Stability of the feedback loop, however, depends in part on the loop filter. The electronic characteristics of the loop filter, in turn, often depend significantly on manufacturing parameters. As a result, the same loop filter design may result in a stable feedback loop when manufactured with one process but an unstable loop when manufactured by another. It is difficult to produce a single loop filter design for use with all manufacturing processes, and the design of the loop filter typically must be optimized on a process by process basis.
The delay-locked loop generates a synchronized local clock by delaying the incoming reference clock by an integer number of periods. More specifically, the buffers, voltage level converters, etc. of the integrated circuit introduce a certain amount of delay. The delay-locked loop introduces an additional amount of delay such that the resulting local clock is synchronous with the incoming reference clock. This approach avoids the stability problem inherent in the phase-locked loop approach. Delay-locked loops, however, have a disadvantage of narrow frequency range. The delay-locked loop adjusts the amount of additional delay in order to achieve the desired synchronization, but this adjustment is essentially a phase adjustment. The delay-locked loop lacks any significant frequency adjustment, thus limiting the overall frequency range of conventional delay-locked loops.
Accordingly, there is a need for a device which synchronizes local clocks to reference clocks, is robust to variations in the manufacturing process, and can operate over a wide frequency range.